The present invention relates to a buffer control circuit and, more particularly, to a buffer control circuit used for a data processor comprising an operand buffer and an instruction buffer for instruction prefetch.
As shown in FIG. 2, a conventional buffer control circuit comprises an operand buffer 21, an instruction buffer 22, an operand buffer control circuit 23, an instruction buffer control circuit 24, an operand data aligning circuit 15, and an instruction data aligning circuit 16.
Operand data designated by an instruction is read out from a main memory (not shown), and is supplied to the operand buffer 21 as main memory readout data 101. In response to an operand data storage command signal 102 supplied together with the readout data 101, the operand buffer 21 stores the readout data 101 at an address designated by an operand buffer write address 112 from the operand buffer control circuit 23.
The operand data stored in the operand buffer 21 is read out from an address designated by an operand buffer read address 114 from the operand buffer control circuit 23, and is output to the operand data aligning circuit 15 as an operand buffer output signal 108.
In response to an operand data alignment command signal 110 from the operand buffer control circuit 23, the operand data aligning circuit 15 aligns an operand buffer output signal 108 from the operand buffer 21 and outputs an alignment result to the operating unit as operand data 106.
Instruction data is read out from the main memory and is supplied to the instruction buffer 21 as the main memory readout data 101. In response to an instruction data storage command signal 103 supplied together with the readout data 101, the instruction buffer 22 stores the readout data 101 at an address designated by an instruction write address 113 from the instruction buffer control circuit 24.
When an instruction decode signal 104 input to the instruction buffer control circuit 24 represents an instruction other than a branch instruction, the instruction data stored in the instruction buffer 22 is read out from an address designated by an instruction buffer read address 115 from the instruction buffer control circuit 24, and is output to the instruction data aligning circuit 16 as an instruction buffer output signal 109.
In response to an instruction data alignment command signal 111 from the instruction buffer control circuit 24, the instruction data aligning circuit 16 aligns the instruction buffer output signal 109 from the instruction buffer 22, and outputs the alignment result to the operating unit as instruction data 107.
If the instruction decode signal 104 supplied to the instruction buffer control circuit 24 represents a branch instruction, and a branch condition satisfaction signal 105 from the operating unit represents that a given condition is not satisfied, the instruction buffer control circuit 24 outputs the instruction buffer read address 115 to the instruction buffer 22 and outputs the instruction data alignment command signal 111 to the instruction data aligning circuit 16.
In response to the instruction data alignment command signal 111 from the instruction buffer control circuit 24, the instruction data aligning circuit 16 aligns the instruction buffer output signal 109 from the instruction buffer 22, and outputs the alignment result to the operating unit as the instruction data 107.
If the branch condition satisfaction signal 105 represents that a given condition is satisfied, the instruction buffer control circuit 24 initializes the instruction buffer write address 113 and the instruction buffer read address 115 and outputs a read command signal 116 for reading out instruction data at a branch destination to the main memory.
After the instruction data at the branch destination is read out from the main memory in response to the read command signal 116 and is stored in the instruction buffer 22, the instruction buffer read address 115 is output from the instruction buffer control circuit 24 to the instruction buffer 22. At the same time, the instruction data alignment command signal 111 is output to the instruction data aligning circuit 16, and the instruction buffer output signal 109 supplied from the instruction buffer 22 and aligned by the instruction data aligning circuit 16 is output to the operating unit as the instruction data 107.
In such a conventional buffer control circuit, when a branch instruction is to be processed, since instruction data at a branch destination cannot be obtained from the main memory until satisfaction of a given branch condition is confirmed by the branch condition satisfaction signal 105 from the operating unit, execution efficiency of branch instructions is decreased.